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LS3C5000L Specification

Frequency

2.0GHz–2.2GHz

Computing speed

560GFLOPS

Number of cores

16

Processor core

based on LoongArch; supporting 128/256-bit vector instructions; 4-issue out-of-order execution; 4 fixed-point units, 2 vector units, and 2 memory access units High-speed cache: Each processor core contains a 64KB private L1 instruction cache and a 64KB private L1 data cache. Each processor core contains a 256KB private L2 cache. Every four

High-speed cache

Each processor core contains a 64KB private L1 instruction cache and a 64KB private L1 data cache. Each processor core contains a 256KB private L2 cache. Every four processor cores share a 16MB L3 cache, which is 64MB in total.

Memory controller

four 72-bit DDR4-3200 controllers; supporting ECC

High-speed I/O

four HyperTransport 3.0 controllers; supporting CC-NUMA

Other I/O

1 SPI, 1 UART, 3 I2Cs, and 16 GPIO interfaces

Power management

supporting dynamic shutdown of the clocks of main modules; supporting dynamic frequency scaling in main clock domains; supporting dynamic voltage scaling in main voltage domains

Typical power consumption

130W@2.2GHz

LS3C5000L Manual

LS3C5000L Application